[Libre-soc-isa] [Bug 924] potential major opcode allocation for SVP64

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=924

--- Comment #15 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
bit 6 and 7 you have to decipher from EXT001 Power ISA Public v3.1 1.6.3

* bit 6: old / new
* bit 7: memory / register

Paul and Brad suggested using a similar encoding for SVP64(*)

* bit 6: old / new
* bit 7: scalar / vector

the problem is, that takes up 100% of a Primary Opcode and we need to
reduce that allocation a **LOT**.

there is nothing we can do about EXT000-063 (bit6=1) that just has to be 50% of
the PO.

but we *can* limit the amount of space needed in EXT2nn (bit6=0) by forcing
the top two bits to be 0b11xxxx, which has the effect of forcing
numbering to be in the range EXT248-263.

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