[Libre-soc-isa] [Bug 664] design SVP64 branch instructions (sv.bc)

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=664

--- Comment #8 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #7)
> imho adding sv context switching within a sv vertical loop is too complex.

my feeling here it's going to be attempted whether we like it or not.
therefore, it's down to us to explore that space, in advance, and to
make it a smooth rather than a rough ride.

if a lot of mfspr/mtspr instructions on SVSTATE have to be used, that's
a rough ride.  mfspr SVSTATE bclr mtspr SVSTATE repeat repeat repeat repeat.

the concept comes from the ZOLC "stack", and with the low-level HDL
blocks being literally identical in ZOLC as they are for Matrix REMAP
it's conceptually not that hard.

full ZOLC on the other hand: *that's* hard, and i definitely don't want
to go that route, it'll take months to understand (just ZOLC alone)

saving of SVSTATE for stack/nesting purposes during a Vertical-First function,
in order to perform a localised Horizontal-First localised piece of work,
was always inevitable.  normally it's "only" the PC that's saved on-stack,
because that's the primary context.

now SVSTATE is part of that primary context.

it's not that hard to conceptualise, especially given that SVSTATE is
effectively a sub-program-counter: this has been in the documentation
and in presentations on SV for over two years as an introductory
statement.

-- 
You are receiving this mail because:
You are on the CC list for the bug.