[Libre-soc-isa] [Bug 553] svp64 register mapping to accomidate AltiVec vectors expanding fp registers

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=553

--- Comment #12 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #11)
> future problem, not our problem, VSX is completely out of scope.
> we are not expanding SVP64 FP registers for the purposes of fitting
> with VSX. any attempt to do so will poison SVP64.
> SVP64 registers are expanded in a way that is easy to understand
> and works with GPUs.

well, vsx registers are used for 128-bit scalar operations (f128, i128), so,
unless you want to propose a completely separate set of 128-bit arithmetic
operations (which imho will never fly with the openpower foundation because
*they already have them*), by your deciding to not make any attempt to
interoperate with vsx registers, we are effectively permanently locked out of
128-bit arithmetic instructions, which imho is foolish.

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