[Libre-soc-isa] [Bug 553] svp64 register mapping to accomidate AltiVec vectors expanding fp registers

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=553

--- Comment #11 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
future problem, not our problem, VSX is completely out of scope.
we are not expanding SVP64 FP registers for the purposes of fitting
with VSX. any attempt to do so will poison SVP64.
SVP64 registers are expanded in a way that is easy to understand
and works with GPUs.

Intel and VSX retrofitted FP into a quadrant of Packed SIMD registers
in a way that has absolutely nothing to do with Vector ISAs, and is
based entirely on 32 FP / 64 VSX/AVX numbering.  that is THEIR PROBLEM
to deal with the fall-out of that decision.

plwase drop this discussion, we are NEVER going to poison or damage
SVP64 for the purposes of fitting with a legacy 20 year old broken
concept.

if people want to do harm by retrofitting with a broken Packed SIMD ISA
concept they are perfectly well at liberty to do so on their own time
and at their own expense.

we have TOO MUCH ELSE TO DO.

any further discussion is wasting our time, energy and resources.

please drop this matter and consider it permanently closed.

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