[Libre-soc-isa] [Bug 615] talk to binutils and gcc developers about acceptable sv assembly format

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=615

--- Comment #2 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
from the above, we can evaluate an idea kindly suggested by Segher, to fulfil
requirement (5): that SVP64 augmentation of registers as Vector or scalar be
done as an additional argument.

instead of:

     svadd 5.v, 6.v, 7.v

it would be:

     svadd 5, 6, 7, 1, 1, 1
or   svadd 5, 6, 7, 0b111


the issue with this is that it breaks requirement (2), in multiple ways.

firstly, it gives the impression that SV is adding extra arguments to the
*scalar* v3.0B instruction, when it is not (SVP64 is *augmenting* the
registers)

secondly: some instructions have optional argiments as scalar (sync is an alias
for sync 0).  if Vectorised it becomes ambiguous as to whether the optional
argument applies to the underlying scalar operation or to the Vectorisation
Augmentation/Embedding.

thirdly: adding new scalar instructions becomes problematic, in that every new
instruction added, by having this lack of abstraction, now has to be evaluated
carefully by inventing a new syntax not just for the scalar variant but also
for the Vectorised variant.

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