[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #37 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/compldst_multi.py;h=8e9f4ec35718541824a78e3ab857dfbf8f307378;hb=1c274daab0955fa0e1cb98c4fe43709b7f795c99#l500

byte reversal for store is slightly further down.  the byte mode is a property
of memory, not of the ALUs, regfiles or data paths between them.

alexandre: there is no pretending (or there is, but in a clear definitive
sense).  it is much stronger than that.  there is a choice (a declaration),
"data in BE will not be tolerated in ALUs or regfiles, it will be converted to
LE, stored as LE, processed as LE and only on moving back to memory converted
to BE".

both LibreSOC and microwatt make this decision.

the conversions are done IMMEDIATELY the data is read from memory, where the
width is known, and the conversion on store is done at the last minute as well.

no data is EVER permitted to enter not one single ALU or regfile without first
being converted to LE.

processing only occurs in LE ALUs.

if this had not been done it would be necessary to have duplicate ALUs: one for
LE, one for BE. or, byteswapping would need to be a property of the regfile.
clearly that is absurd so the decision has been made to convert and work
internally as LE.

this works because it is only the memory interface that has the ordering.

to reiterate: it is *Load and Store* that have the LE/BE property.

does this provide you with the missing information to clarify?

if not then i need to understand what it is that you are missing, so that it
can be made clear.

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