[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #36 from Alexandre Oliva <oliva at libre-soc.org> ---
> let us assume LE mode

doh, you can't show it works the same way in both endiannesses by assuming it's
the one that gets you the result you one.  you have to work it out in both. 
and if you had, you'd have realized that the answer that you say we *must* get
is not the one we get with the current specifications.

Namely, with BE, what you load into r4 is 0x0102030405060708, and then, if you
iterate over the bytes as a vector in the order you've decided, that starts at
the LSB, you visit 0x08 first, then 0x07, till 0x01, then you go to 0x00, 0x0f,
0x0e, ..., 0x09.

Which maybe fits in with the notion of "let's pretend it's all LE", but... 
it's not how vectors work in BE mode on ppc.  and, what's more, it's not how
you stated you wanted vectors to work in svp64 in BE mode.

if your approach to looking into endianness issues is "let's pretend it's LE",
I strongly recommend stating that we'll only support LE period, because these
things don't get right just by not looking into them.  that's better than
getting dysfunctional hardware out there, and then having to either break
compatibility or, worse, maintain it indefinitely, with stuff that hasn't been
thought through.

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