[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #38 from Alexandre Oliva <oliva at libre-soc.org> ---
luke, please do work out the example in BE as you did in LE.
it's not me the one who needs the clarification.
your answer to the question directly contradicts what you claim we do and can't
change.  one of them has to give.

uint8_t foo[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };

; r3 points to foo
  ld r4, 0(r3)
  ld r5, 8(r3)
  setvli r0, 16
  svp64 elwidth_src=8-bit mv r6.s, r4.v  

should r6 be 1, or 8, or should it depend on endianness?

remember, you answered it had to be 1, but the byte-order reversal from BE to
LE at the loads will place the 1 at the wrong end of the vector register for it
to be the first 8-bit element per your own description of the expected and
intended behavior.

-- 
You are receiving this mail because:
You are on the CC list for the bug.