[Libre-soc-isa] [Bug 533] design new CR instructions suitable for predication

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=533

--- Comment #2 from Jacob Lifshay <programmerjake at gmail.com> ---
What I was thinking of is more like an instruction that reads a single 4-bit CR
field and writes a 1 or a 0 to an integer register based on if the 4-bit CR
field matches some condition. That instruction when vectorized would produce a
bit-vector in the integer register with 1 bit per element.

The instruction would have a 4-bit immediate with bits a, b, c, and d. The
output of the instruction would be:
(a & cr_lt) | (b & cr_eq) | (c & cr_gt) | (d & cr_unordered)

(icr if that's the right order for cr bits, but you get the idea).

This allows producing any pattern of ones and zeros assuming the cr is set to
the result of an integer or fp compare op. For int compares, we set d = 0. For
int/fp compares, the rest of the bits select the output value that should be
generated for a particular compare result:
lt -> output = a
eq -> output = b
gt -> output = c
unordered (fp only) -> output = d

-- 
You are receiving this mail because:
You are on the CC list for the bug.