[Libre-soc-isa] [Bug 533] design new CR instructions suitable for predication

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=533

--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
we could add another instruction to generate a cr vector from a bit-vector: we
could set each cr to gt if the integer bit is 1 and to eq if the integer bit is
0. This should be sufficient for 99.9% of the cases where we just want values
in the cr fields, but don't care too much what exact values are put there, the
rest can use mtcr or this new instruction combined with cr-logic ops.

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