[Libre-soc-isa] [Bug 533] design new CR instructions suitable for predication

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=533

Luke Kenneth Casson Leighton <lkcl at lkcl.net> changed:

           What    |Removed                     |Added
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           Assignee|lkcl at lkcl.net               |programmerjake at gmail.com

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
hmm i am curious.  crand and cror etc. if they are used to target one bit of
the same CR as src1 and another bit of the same CR as src2, one is the "eq
zero" bit and the other say the "+ve" bit, and the dest is say the OV bit of
the same CR, that computes GE in the case of cror and err... GT in the case of
crand.

now if those are vectorised that would produce a vector of GT/GE operations,
would it not?

jacob did you have any other type of CR operations in mind that do not fit into
this category?

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