[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #26 from Alexandre Oliva <oliva at libre-soc.org> ---
jacob, now add 0x80 to each of the vector elements and tell me whether r6
should end as 0x81 or -1 ;-)

(i.e., zero or sign extension :-)

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