[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Dec 31 02:28:10 GMT 2020


--- Comment #26 from Alexandre Oliva <oliva at libre-soc.org> ---
jacob, now add 0x80 to each of the vector elements and tell me whether r6
should end as 0x81 or -1 ;-)

(i.e., zero or sign extension :-)

You are receiving this mail because:
You are on the CC list for the bug.

More information about the Libre-SOC-ISA mailing list