[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #25 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Alexandre Oliva from comment #24)
> the point is, we have to make a choice here.  do we choose
> 
> a) compatibility with the memory/data endianness selected for the system,
> and set the iteration order in sub-register vector elements to match, or 

I think option a makes waay more sense. it also *does* give a performance
advantage since bitcasts compile to 0 instructions.

the code Alexandre wrote should *always* put 1 in r6, even if the high bytes of
r6 weren't zero before (combining both scalar-means-full-register with
memory-endian for registers).

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