[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #27 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Alexandre Oliva from comment #26)
> jacob, now add 0x80 to each of the vector elements and tell me whether r6
> should end as 0x81 or -1 ;-)
> 
> (i.e., zero or sign extension :-)

that depends on the instruction (icr if we added a signed/unsigned bit to
svp64, we should). For mv encoded using add, it would be sign extension (i
guess), for mv encoded using or, it would be zero extension.

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