[Libre-soc-dev] Orangecrab progress

[Tobias Platen]

I tried to get a uart output in icarus verilog, that did not work for
an unknown reason. Knowing that the uart works in ls2 and that the core
boots from the right location, I flashed the orangecrab with the latest
version of ls2. As expected it shows the Soc features, but DRAM fails:

Soc signature: 00010001F00DAA55  Soc features: UART DRAM 
DRAM init... initseq
done
MR profile: 00000B20 00000806 00000200 00000000
Rdly
p0: 00000000
Rdly
p1: 00000000
Auto calibrating... find minfailed
done
Auto calibration profile:p0 rdly:00000007 p1 rdly:00000007
Reloading built-in calibration profile...DRAM test... 
fail : *(0x00000000) = 00000000
fail : *(0x00000004) = DEAF0000
fail : *(0x00000008) = DEAF0004
fail : *(0x0000000C) = DEAF0008
fail : *(0x00000010) = 00000000
fail : *(0x00000014) = DEAF0010
fail : *(0x00000018) = DEAF0014
fail : *(0x0000001C) = DEAF0018
fail : *(0x00000020) = 00000000
fail : *(0x00000024) = DEAF0020
fail : *(0x00000028) = DEAF0024
Test canceled (more than 10 errors)
done