[Libre-soc-dev] change sv ld/st to allow non-zero immediates for unit-strided load/store

[lkcl]

On Wednesday, October 12, 2022, Jacob Lifshay <programmerjake at gmail.com>
wrote:

> ok, though I think it can fit,

regardless of whether it can fit, it's "a change requiring
major review and disruption".

i am pretty fed up of constantly revising LDST.

>though am not sure because the LD/ST
> immediate modes pseudocode isn't very clear:

now you know why i don't want it changed.

>
https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/ldst.mdwn;h=eb32548ed1d5ea665dba1f27bf61f394356cb1a1;hb=HEAD#l120
>>      if RA.isvec:
>>         svctx.ldstmode = indexed
>>     elif els == 0:
>>         svctx.ldstmode = unitstride
> if immediate can be != 0 for unitstride here, that's exactly what we need.

well, read the definition of unitstride:

   elif svctx.ldstmode == unitstride:
     # unit stride mode
     srcbase = ireg[RA]
     offs = immed + (i * op_width) # j*op_width for ST

beyond that, a simple scalar LD-imm can be used and followed
up by a vsplat-MV or other vsplat operation.

LD/ST has been so horrendous and so complex to evaluate
that i don't want to touch it any more.


>>     elif immediate != 0:
>>         svctx.ldstmode = elementstride
> missing cases at the end. please fix.

some time in the next several months, when i have time
to go over it for about the 50th to 60th time in 2 years...
yes.

initial thoughts though are that you may be missing the
point: VSPLAT is an inherent artefact of looping, whereas
those ldstmodes are not.

l.

l.