[Libre-soc-dev] change sv ld/st to allow non-zero immediates for unit-strided load/store

[Jacob Lifshay]

On Tue, Oct 11, 2022 at 4:50 PM lkcl <luke.leighton at gmail.com> wrote:
ok, we can skip using RA=r1 as a mode selector.

> there are an alarmingly high number of modes as it is, LDST has
> undergone approximately seven major design revisions, each time
> losing one mode over another, making several unsatisfactory
> compromises.

ok, though I think it can fit, though am not sure because the LD/ST
immediate modes pseudocode isn't very clear:
https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/ldst.mdwn;h=eb32548ed1d5ea665dba1f27bf61f394356cb1a1;hb=HEAD#l120
>      if RA.isvec:
>         svctx.ldstmode = indexed
>     elif els == 0:
>         svctx.ldstmode = unitstride
if immediate can be != 0 for unitstride here, that's exactly what we need.
>     elif immediate != 0:
>         svctx.ldstmode = elementstride
missing cases at the end. please fix. please add LD-VSPLAT to the
if/else sequence.

Jacob