[Libre-soc-dev] Hello

[lkcl]

On March 25, 2022 3:44:26 PM UTC, zemaye <zemaye at protonmail.com> wrote:
>Hello, I'm zemaye and would like to help. I have read through the terms
>of the charter and agree to it and look forward to helping out where I
>can.

hiya zemaye that's fantastic, welcome.

>I enjoy studying operating systems and compilers. I'm proficient in
>python and OO design and I'm familiar with digital design concepts. C++
>is fun too.

nice. yeah i never knew VLSI but learned it from doing Electronics, PCB layout, and gate level design, i meam ultimately it's just levels of detail in the end, how far down the rabbithole you are prepared to dive.

>I've been working through the getting started documentation. I have
>debian set up with mucho ram and the HDL workflow appears to be
>working.

use devscripts page, save some time
https://libre-soc.org/HDL_workflow/devscripts/

we have people often take 3+ days without the devscripts!

do note i just updated hdl-tools-yosys because only yosys-0.13 works at the moment.

https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=hdl-tools-yosys;hb=HEAD

for example only by using 0.13 could we get an ECP5 bitstream working. sigh.

> I have one of these orangecrab boards as well. Now I'm reading
>through the nmigen documentation.

i do advocate to people, to use yosys "show top" on the design. read_ilang or read_verilog then view it 2D and the graphviz has signal names shows connections and after doing that for 6 months the nmigen HDL started to make sense (without the graph)

>Nice to meet you all.

you too

warmest,

l.