[Libre-soc-dev] daily kan-ban update 05jun2022

[Cesar Strauss]

After receiving my OrangeCrab, I spent the last few weeks studying it. I 
ran Litex, microPython, and even Linux on Litex-Vexriscv.

Moving from Litex/Migen towards nMigen, I've successfully tried LUNA, so 
I can talk to the board through Serial-USB, much like Litex does 
already. No need for extra cables, and, more important for me, no 
soldering...

I see that nMigen support for ls2/DRAM3 seems to be currently a problem 
(bug #801), as well as nmigen-boards support for the OrangeCrab (issue 
#2). So, lately I've been:

1) comparing nmigen-boards pin definitions with OrangeCrab schematics 
and Litex
2) reading the DRAM chip datasheet and ECP5 technical notes
3) comparing the Gram implementation with Litedram and the ECP5 guidelines.

I intend at least to send a pull request to improve nmigen-boards 
support for the OrangeCrab (aligning it with Litex). Maybe, it would be 
a good idea for me to try the headless Gram example, to have less unknowns.

Regards,

Cesar