[Libre-soc-dev] daily kan-ban update 03jul2022

[Cesar Strauss]

Em 05/07/2022 13:54, Cesar Strauss escreveu:
> Em 04/07/2022 19:02, Cesar Strauss escreveu:
>> Em 03/07/2022 15:49, Tobias Platen via Libre-soc-dev escreveu:
>>> orangecrab WERROR: Failed to find a route for arc 2 of net 
>>> ddrphy_ddr3_0__a__o_fclk.
> 
> The LiteX target file for the OrangeCrab has an "ECLKBRIDGECS":
> 
> https://github.com/litex-hub/litex-boards/blob/32f507cc08aa4b969d952143f9fc4fdf82228951/litex_boards/targets/gsd_orangecrab.py#L109 
> 

The attached diff for ls2 seems to route fine for the OrangeCrab, 
generating a bitstream. Being a bit cautious, I did not try programming 
it yet (will carefully try the headless Gram example, first, to gain 
confidence).

The diff unconditionally inserts a ECLKBRIDGECS (following LiteX), 
disables SPI, and re-enables abc9 logic packing, to help meet timing 
(see https://github.com/Ravenslofty/yosys-cookbook/blob/master/ecp5.md).

This work in progress surely needs adjusting and review, before properly 
going into ls2 and gram.

Regards,

Cesar
-------------- next part --------------
diff --git a/src/ecp5_crg.py b/src/ecp5_crg.py
index 403ff7d..43c54c6 100644
--- a/src/ecp5_crg.py
+++ b/src/ecp5_crg.py
@@ -204,8 +204,13 @@ class ECP5CRG(Elaboratable):
         # create PLL clocks
         pll.create_clkout(ClockSignal(cd2x_ub), 2*freq)
         if esyncb:
+            sys2x_clk_ecsout = Signal()
+            m.submodules["%s_eclkbridgecs" % cd] = Instance("ECLKBRIDGECS",
+                    i_CLK0 = ClockSignal(cd2x_ub),
+                    i_SEL  = 0,
+                    o_ECSOUT = sys2x_clk_ecsout)
             m.submodules["%s_eclksyncb" % cd] = Instance("ECLKSYNCB",
-                    i_ECLKI = ClockSignal(cd2x_ub),
+                    i_ECLKI = sys2x_clk_ecsout,
                     i_STOP  = 0,
                     o_ECLKO = ClockSignal(cd2x))
         else:
diff --git a/src/ls2.py b/src/ls2.py
index 0e72d47..8e64064 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -958,7 +958,7 @@ def build_platform(fpga, firmware):
         spi_0_pins = platform.request("spi_0", 0)
 
 
-    if platform is not None and \
+    if False and platform is not None and \
        fpga in ['orangecrab']:
        # spi_flash_mosi   <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
        # spi_flash_miso   <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
@@ -1100,8 +1100,8 @@ def build_platform(fpga, firmware):
     if toolchain == 'Trellis':
         # add -abc9 option to yosys synth_ecp5
         #os.environ['NMIGEN_synth_opts'] = '-abc9 -nowidelut'
-        #os.environ['NMIGEN_synth_opts'] = '-abc9'
-        os.environ['NMIGEN_synth_opts'] = '-nowidelut'
+        os.environ['NMIGEN_synth_opts'] = '-abc9'
+        #os.environ['NMIGEN_synth_opts'] = '-nowidelut'
 
     if toolchain == 'yosys_nextpnr':
         # add --seed 2 to arty a7 compile-time options