[Libre-soc-dev] daily kan-ban update 03jul2022

[Tobias Platen]

On Tue, 2022-07-05 at 12:08 -0500, Timothy Pearson via Libre-soc-dev
wrote:
> 
> 
> ----- Original Message -----
> > From: "Libre-Soc General Development"
> > <libre-soc-dev at lists.libre-soc.org>
> > To: "Libre-Soc General Development"
> > <libre-soc-dev at lists.libre-soc.org>
> > Cc: "cestrauss" <cestrauss at gmail.com>
> > Sent: Tuesday, July 5, 2022 11:54:02 AM
> > Subject: Re: [Libre-soc-dev] daily kan-ban update 03jul2022
> 
> > Em 04/07/2022 19:02, Cesar Strauss escreveu:
> > > Em 03/07/2022 15:49, Tobias Platen via Libre-soc-dev escreveu:
> > > > orangecrab WERROR: Failed to find a route for arc 2 of net
> > > > ddrphy_ddr3_0__a__o_fclk.
> > > 
> > > Maybe some attribute is missing, on the ls2 clock generator, or
> > > the
> > > PLL. I'll compare with LiteX / LiteDRAM, and see if I can spot
> > > the
> > > difference.
> > > 
> > 
> > The LiteX target file for the OrangeCrab has an "ECLKBRIDGECS":
> > 
> > https://github.com/litex-hub/litex-boards/blob/32f507cc08aa4b969d952143f9fc4fdf82228951/litex_boards/targets/gsd_orangecrab.py#L109
> > 
> > The LiteX target file for the Versa doesn't have it.
> > 
> > Neither does our ecp5_crg.py, on ls2 (for any target).
> > 
> > From the "ECP5 and ECP5-5G High-Speed I/O Interface" manual:
> > 
> > "Edge Clocks (ECLK) are high-speed, low-skew I/O dedicated clocks.
> > They
> > are arranged in groups of two per I/O bank on the left and right
> > sides
> > of the device. Each of these Edge Clocks can be used to implement a
> > high-speed interface. There is an Edge Clock Bridge (ECLKBRIDGECS)
> > that
> > allows you to build large interfaces by bridging the Edge Clocks
> > from
> > one bank to the other on the same side or from one side to the
> > other side."
> > 
> > I guess the Versa has all DDR3 pins on just one bank, while the
> > OrangeCrab has them on different banks, thus needing an
> > ECLKBRIDGECS.
> > 
> > Cesar
> 
> Acrtic Tern uses the same overall design, since it talks to two
> different DRAM devices per FPGA (wide data bus):
> 
> https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-litex/litex-boards/-/blob/master/litex_boards/targets/rcs_arctic_tern_bmc_card.py#L121
> 
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I'll interested in that, so I will have a look at that.