[Libre-soc-dev] proposal of change of register name convention in SVP64

[Luke Kenneth Casson Leighton]

On Fri, Jul 1, 2022 at 1:07 PM Dmitry Selyutin <ghostmansd at gmail.com> wrote:

> That is, whenever the register is expected, even if it's scalar, make
> one write say %r117 instead of 117, and %v:r117 instead of v:117.
> That'd make parsing even simpler.

makes it clear that it's not "normal" register naming...
is a hell of a lot of work changing 160+ pages of specification
and existing unit tests...
which has to be done anyway given the change to vector-naming.
sigh.

sure, why not :)

l.