[Libre-soc-dev] daily kan-ban update 04jan2022

[Tobias Platen]

When I run issuer_verilog.py I get the following, I think I forgot a
make update or something:

ROW_SIZE 8
ROW_PER_LINE 8
BRAM_ROWS 128
NUM_WAYS 4
  DCache Layout:
 |.. -----------------------| REAL_ADDR_BITS (56)
  ..         |--------------| SET_SIZE_BITS (10)
  ..  tag    |index|  line  |
  ..         |   row   |    |
  ..         |     |---|    | ROW_LINE_BITS (3)
  ..         |     |--- - --| LINE_OFF_BITS (6)
  ..         |         |- --| ROW_OFF_BITS  (3)
  ..         |----- ---|    | ROW_BITS      (7)
  ..         |-----|        | INDEX_BITS    (4)
  .. --------|              | TAG_BITS      (46)

Dcache TAG 46 IDX 4 ROW_BITS 7 ROFF 3 LOFF 6 RLB 3
index @: 6-10
row @: 6-3
tag @: 10-56 width 48
TAG_RAM_WIDTH 192
    TAG_WIDTH 48
     NUM_WAYS 4
    NUM_LINES 16
BRAM_ROWS       = 128
INDEX_BITS      = 4
INSN_BITS       = 1
INSN_PER_ROW    = 2
LINE_SIZE       = 64
LINE_OFF_BITS   = 6
LOG_LENGTH      = 0
NUM_LINES       = 16
NUM_WAYS        = 4
REAL_ADDR_BITS  = 56
ROW_BITS        = 7
ROW_OFF_BITS    = 3
ROW_LINE_BITS   = 3
ROW_PER_LINE    = 8
ROW_SIZE        = 8
ROW_SIZE_BITS   = 64
SET_SIZE_BITS   = 10
SIM             = 0
TAG_BITS        = 46
TAG_RAM_WIDTH   = 184
TAG_BITS        = 46
TLB_BITS        = 6
TLB_EA_TAG_BITS = 46
TLB_LG_PGSZ     = 12
TLB_PTE_BITS    = 64
TLB_SIZE        = 64
WAY_BITS        = 2
Namespace(output_filename='/tmp/issuer.v', xics=True, lessports=True,
core=True, mmu=False, pll=False, enable_testgpio=False,
enable_sram4x4kblock=False, debug='jtag', svp64=True)
mmu False
nocore False
regreduce True
gpio False
sram4x4kblock False
xics True
use_pll False
debug jtag
SVP64 True
Traceback (most recent call last):
......
FileNotFoundError: [Errno 2] No such file or directory:
'/path/to/soc/src/soc/config/../../../pinmux/ls180/litex_pinpads.json'