[Libre-soc-dev] daily kan-ban update 23feb2002

[lkcl]

On February 22, 2022 4:28:08 PM UTC, lkcl <luke.leighton at gmail.com> wrote:

>i am investigating the gram controller which using the icarus verilog
>simulation of a micron ddr3 IC i can see has data synchronisation
>issues.  i have however yet to find exactly where those are.

today i fixed two things

1) the update to the ECP5 clock reset generator (CRG) for nmigen turned out to be faulty but fascinatingly the verilog models supplied by lattice are accurate enough to do proper simulations under icarus and i was able to find the problem (inverted reset being one of them)

this then in turn actually got the icarus verilog DDR3 simulation to pass 100%

2) to the nmigen gram controller simulation ("FakePhy" he calls it) written by Jean Thomas i was able to add some previously missing CSRs, just enough to make wishbone reads and writes succeed

this in turn allowed me to see gtkwave traces that failed and i was able to spot that cache-inhibiting had not been wired up in the LDST unit!

the result of that was that the D-Cache was trying to load a batch of QTY 8 64-bit data, hitting a wishbone Memory Mapped peripheral that only had QTY 3 32-bit values!

clearly this is bad.

now sorted.


tomorrow i will continue bashing the DRAM startup code into shape, currently the stack is being overwritten.

l.