[Libre-soc-dev] effect of more decode pipe stages on hardware requirements for execution resources for OoO processors

[Jacob Lifshay]

On Tue, Feb 15, 2022, 18:44 Jacob Lifshay <programmerjake at gmail.com> wrote:

> that said, essentially every useful 4-instruction loop will have this
> problem because it's intrinsic to the concept of having loop counters that
> are incremented each iteration, unless we build a cpu that can do loop
> unrolling on-the-fly (definitely well beyond what a OoO cpu normally does).
>

loop unrolling and expression tree rebalancing:
goes from something like (ctr1-4 are all renamed versions of the ctr
register):
ctr2 <- ctr1 + 1
ctr3 <- ctr2 + 1
ctr4 <- ctr3 + 1
ctr5 <- ctr4 + 1
to, after expression rebalancing:
ctr2 <- ctr1 + 1
ctr3 <- ctr1 + 2
ctr4 <- ctr1 + 3
ctr5 <- ctr1 + 4

Jacob

>