[Libre-soc-dev] effect of more decode pipe stages on hardware requirements for execution resources for OoO processors

[Jacob Lifshay]

luke & I were arguing about wether additional decode pipe stages
necessitate more reorder buffers, rename registers, and other execution
hardware buffers. I made this wiki entry with pipe timing diagrams to
support my position that, ignoring branch misprediction, no additional
execution resources are needed.

https://libre-soc.org/openpower/openpower/sv/effect-of-more-decode-stages-on-reg-renaming/

Jacob