[Libre-soc-dev] SVP64 Vectorised add-carry => big int add

[lkcl]

On April 17, 2022 11:38:27 AM UTC, lkcl <luke.leighton at gmail.com> wrote:

>how about using RC as the CARRY?

nope that doesn't work, RC is a Vector not scalar.  4-in 2-out is QTY 6 64-bit operands, there's just no way that will be accepted.  no, using an SPR does not work, it still requires Dependency Tracking plus needs saving on contextswitch. the more of those the worse latency becomes.

we have to find another way.

see end of:

https://libre-soc.org/openpower/sv/bitmanip/appendix/

how about storing the 128-bit mul-add in a *pair* of vectors, 3-in 2-out just like DCT/FFT: RT and RT+VL

a second followup instruction can perform the carry-adds with corrections.

how would that look?

l.