[Libre-soc-dev] SVP64 Vectorised add-carry => big int add

[lkcl]

On April 17, 2022 9:54:14 AM UTC, Jacob Lifshay <programmerjake at gmail.com> wrote:

>turns out, after some checking with 4-bit words, afaict the correct
>algorithm for mrsubcarry is:
># for big_c - big_a * word_b
>result <- RC + ~(RA * RB) + CARRY
>result_high <- HIGH_HALF(result)
>if CARRY <= 1 then # unsigned comparison
>    result_high <- result_high + 1
>end
>CARRY <- result_high
>RT <- LOW_HALF(result)

ok i see where this is going.  but, 4-op in, that's not going to fly.  plus, RC will be added multiple times in the loop.

how about using RC as the CARRY?

    result <- RC + ~(RA * RB)
    result_high <- HIGH_HALF(result)
    if RC <= 1 then # unsigned comparison
       result_high <- result_high + 1
    end
    RC <- result_high
    RT <- LOW_HALF(result)

that i think would loop well, it is {3-in 2-out} which is in line with the other FFT and DCT butterfly ops, and works perfectly well with the mapreduce setting. which isn't actually mapreduce, it just switches off the normal loop-termination if a result is scalar.

am recording these here btw
https://libre-soc.org/openpower/sv/bitmanip/appendix/

l.