[Libre-soc-dev] Testing Libre-SoC 0.18um test chip.

[lkcl]

On Fri, Sep 24, 2021 at 10:46 AM Staf Verhaegen (FibraServi)
<staf at fibraservi.eu> wrote:

> > i've also asked Roberto Innocenti of PowerPC-Notebook if he has
> > time / equipment.
>
> OK, so what I understand is that we reserve (some) budget for equipment
> for both Luke and Manuel. I think easiest is if this would be invoiced
> to FIbraServi directly. I may also need some for shipping, import taxes etc.

cool.

> Any proposals for equipment ?

not yet - still making the list.

> I can deliver a socket to Sorbonne University but I only have one to
> spare.

ok.

> Also I think main need is a JTAG debugger compatible with OpenOCD.

standard sub-$10 FT232R, available on Amazon, does perfectly fine.
https://libre-soc.org/HDL_workflow/ECP5_FPGA/

we have all the configs: "adapter driver ft232r" does the job
https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=openocd_ft232.cfg;hb=HEAD

> For testing the external SDRAM interface one may need possibly bread
> board compatible SDRAM chip(s) or a custom PCB with the SDRAM chip on it.

if the ASIC works at all over JTAG with internal DFFs i'd say that's a
huge success.
anything beyond that is a bonus.

>
> For testing I think there are two phases. First is to find out ASAP if
> the chip does something so that NLnet can donate one to the commissioner
> knowing it is not just a piece of junk. Second is more in depth test
> before NLnet deadline.

those have all been extended.

l.