[Libre-soc-dev] Testing Libre-SoC 0.18um test chip.

Staf Verhaegen (FibraServi) staf at fibraservi.eu
Fri Sep 17 10:08:31 BST 2021

Op 17/09/2021 om 05:34 schreef whygee at f-cpu.org:
> Hello list,
> I thought that "DFT" and "codesign" would be used
> but I see that you will receive the proto chips
> and will have waited... and now there are the chips
> with nothing to plug them to. No HW nor SW. 

Originally I was going to do the testing. I have a socket to put the 
chip into and the needed FPGA boards to drive and capture the output. 
Testing was mainly to be done through JTAG interface which I already did 
before and know how to handle. I did not need a custom PCB for testing.

What has changed in the mean time is that I am now too busy.


Chips want to be free.

More information about the Libre-soc-dev mailing list