[Libre-soc-dev] Testing Libre-SoC 0.18um test chip.

[whygee at f-cpu.org]

Hello Luke,
thanks for correcting me.

On 2021-09-17 10:21, lkcl wrote:
> On September 17, 2021 3:34:08 AM UTC, whygee at f-cpu.org wrote:
>> A PCB could have beeen designed and a fake chip tested
>> (so we could debug the test rig before testing the chips)
> this assumes time, knowledge, and resources
I assumed it would be part of the normal procedure.

I'm totally out of the loop in many aspects of the project
which has grown beyond something I could manage,
time-wise but also computer-configuration-wise.

But I have taken some habits in my last projects,
and I suppose you will adopt them too :-)

>> I thought that "DFT" and "codesign" would be used
> this assumes knowledge and training.
I know that this is a "test run" and hope that
the knowledge gained will be reinvested :)

>> but I see that you will receive the proto chips
>> and will have waited... and now there are the chips
>> with nothing to plug them to. No HW nor SW.
> this is not entirely correct, the JTAG loader mechanism has been
> available for months, for testing simulators of several different
> varieties, and on the ECP5.
right.
I forgot that "detail"

> indeed... how best to put this: if this had been known by me (the
> Project Lead) i would have known (past pluperfect tense) to have
> planned for it including putting in a requisite budget.
I suppose so.

> in addition there are not enough people contributing, so (a) how can i
> know and (b) how can it be expected to be done?
you're the lead so you should know right ? :-P

I know you have many hard choices to make and I understand :
getting the chips is the goal.

Now, this is the real deal : how do you know which chips are good ?

> fortunately, Staf, who is knowledgeable but also extremely busy,
> *does* know, so has known to put in a budget request to NLnet through
> Chips4Makers.
Good !

>> Chip design is hard but there are known
>> methods (taught at LIP6) to ensure that the dices are
>> useful immediately after receiving them.
> ... but i did not _go_ to LIP6, i went to Imperial College.
i'm jealous, that sounds way cooler :-)

>> Having a FPGA mockup to fake/emulate the chip
>> is also very precious.
> yes. we have that. tested many months ago.
ah :)

so it's just a matter of plugging things and see what breaks...

You simply need an adapter board, with a ZIF in the middle,
lots of breakout connectors, some controllable power supplies
(to ramp up power and check for shorts and unexpected currents)
some proto area to add features, and JTAG, serial, etc.
As already mentioned, a FPGA can drive signals (one pin per pin),
and an external embedded computer (RPI is great)
can do the highl-level SW testing procedures.


> we would like to avoid soldering of the ASICs at all costs, using
> sockets to ensure they are not damaged by heat.
Of course.
you have 160 chips to test !
If you solder one chip, well... if it breaks you have to desolder etc.
the obvious approach is a ZIF.

When I mentioned soldering, it's soldering the testing boards.

> if that's ok and if you are offering to help that would be great.
At least, we have this discussion and it is a good beginning.
I don't know how I could "practically" help though.
We'll figure it out.

>> Given a full datasheet, creating a flexible and useful
>> breakout board is fairly easy (done it already for other
>> projects).
> there's no datasheet, there will only be one if someone is prepared
> and happy to make one.  we can cover it via the documentation budget.
+1

> as you are aware there is a pinmap.
yes, I think I mentioned it in the beginning.

>> So now what's the plan ?
> put things into a bugreport so they are not lost.
> cumulate knowledge and list of actions.
+1

Other useful details to determine :

* How many test rigs are used, how many want to test it ?

* shouldn't we standardise some things ?

* would we use Raspberry Pi interfaces to drive
the main test signals (power, serial, JTAG, FPGA...)
so anybody can run the show from any type of SSH capable computer ?

I can reuse some existing / tested interface code for RPi,
some test rig tricks from previous projects and do some PCB layout.
My last rig used a ADS7825 (4×16-bit precision ADC) and some
tricks to ramp up the power under tight control from a RPi.

BTW: I can't wait to see those chips.
Good job everybody.

> l.
yg