[Libre-soc-dev] Testing Libre-SoC 0.18um test chip.

lkcl luke.leighton at gmail.com
Fri Sep 17 09:21:26 BST 2021

On September 17, 2021 3:34:08 AM UTC, whygee at f-cpu.org wrote:
>Hello list,
>I'm can't follow all the developments
>(sorry, family & work) and I'm catching up a bit.
>The recent emails surprise me however.
>The chip's pinout is known for months.
>The signals are well controlled.
>A PCB could have beeen designed and a fake chip tested
>(so we could debug the test rig before testing the chips)

this assumes time, knowledge, and resources

>I thought that "DFT" and "codesign" would be used

this assumes knowledge and training.

>but I see that you will receive the proto chips
>and will have waited... and now there are the chips
>with nothing to plug them to. No HW nor SW.

this is not entirely correct, the JTAG loader mechanism has been available for months, for testing simulators of several different varieties, and on the ECP5.

>Normally I would design the test rig simultaneously
>with the chip.

indeed... how best to put this: if this had been known by me (the Project Lead) i would have known (past pluperfect tense) to have planned for it including putting in a requisite budget.

in addition there are not enough people contributing, so (a) how can i know and (b) how can it be expected to be done?

fortunately, Staf, who is knowledgeable but also extremely busy, *does* know, so has known to put in a budget request to NLnet through Chips4Makers.

> Chip design is hard but there are known
>methods (taught at LIP6) to ensure that the dices are
>useful immediately after receiving them.

... but i did not _go_ to LIP6, i went to Imperial College.

>Having a FPGA mockup to fake/emulate the chip
>is also very precious.

yes. we have that. tested many months ago.

>I am equipped for testing (some great scopes and probes)
>and have some experience with FPGA (mainly MicroSemi),
>I love doing PCB layout (I have Eagle7 pro) and soldering.

we would like to avoid soldering of the ASICs at all costs, using sockets to ensure they are not damaged by heat.

if that's ok and if you are offering to help that would be great.

>Given a full datasheet, creating a flexible and useful
>breakout board is fairly easy (done it already for other

there's no datasheet, there will only be one if someone is prepared and happy to make one.  we can cover it via the documentation budget.

as you are aware there is a pinmap.

>So now what's the plan ?

put things into a bugreport so they are not lost.
cumulate knowledge and list of actions.


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