[Libre-soc-dev] Testing Libre-SoC 0.18um test chip.

whygee at f-cpu.org whygee at f-cpu.org
Fri Sep 17 04:34:08 BST 2021

Hello list,

I'm can't follow all the developments
(sorry, family & work) and I'm catching up a bit.
The recent emails surprise me however.

The chip's pinout is known for months.
The signals are well controlled.
A PCB could have beeen designed and a fake chip tested
(so we could debug the test rig before testing the chips)

I thought that "DFT" and "codesign" would be used
but I see that you will receive the proto chips
and will have waited... and now there are the chips
with nothing to plug them to. No HW nor SW.

Normally I would design the test rig simultaneously
with the chip. Chip design is hard but there are known
methods (taught at LIP6) to ensure that the dices are
useful immediately after receiving them.
Having a FPGA mockup to fake/emulate the chip
is also very precious.

I am equipped for testing (some great scopes and probes)
and have some experience with FPGA (mainly MicroSemi),
I love doing PCB layout (I have Eagle7 pro) and soldering.

Given a full datasheet, creating a flexible and useful
breakout board is fairly easy (done it already for other

So now what's the plan ?

On 2021-09-16 17:16, Staf Verhaegen (FibraServi) wrote:
> I think all signal input driving and logic output capturing could be
> combined on one FPGA with enough pins and 3.3V compatibillity.
> (non-exhaustive list of) Things to drive:
>  * clock reference for PLL
>  * Clock multiplier selection for PLL
>  * reset
>  * JTAG
>      o Test outputs directly with boundary scan
>      o drive internal memory mapped peripherals directly without
>        needing CPU
>      o test on-chip memory; load programs into it
>  * GPIO
> greets,
> Staf.

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