[Libre-soc-dev] Testing Libre-SoC 0.18um test chip.

Staf Verhaegen (FibraServi) staf at fibraservi.eu
Thu Sep 16 16:16:23 BST 2021

Op 16/09/2021 om 16:07 schreef lkcl:
> do you know what other components are needed (from scratch)?
> * three PSUs (3.3v, 1.8v, variable for the PLL)
Variable voltage is not needed, one need an ADC to track the internal 
voltage regulation of the PLL. Trying to force the PLL oscillation 
frequency by forcing the voltage on this output to a certain value will 
not work as it is buffered. For a good test it would be nice to measure 
PLL power consumption separately from chip, e.g. have separate power for 
the PLL.
> * and a digital clock of some kind, at least?
> an FPGA i assume may potentially useable to generate clock signals,
> although ensuring they are stable and shielded will be fun over jumper
> cables, a shielded breakout cable should be fine, and it is only what,
> 24 mhz anyway.

You'll also need a logic analyzer of some sort to look at the outputs of 
the chip. Likely also an oscilloscope to look at analog signal(s) when 
digital signal(s) does not make sense.

I think all signal input driving and logic output capturing could be 
combined on one FPGA with enough pins and 3.3V compatibillity.

(non-exhaustive list of) Things to drive:

  * clock reference for PLL
  * Clock multiplier selection for PLL
  * reset
  * JTAG
      o Test outputs directly with boundary scan
      o drive internal memory mapped peripherals directly without
        needing CPU
      o test on-chip memory; load programs into it
  * GPIO


Chips want to be free.

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