[Libre-soc-dev] Testing Libre-SoC 0.18um test chip.

Andrey Miroshnikov andrey at technepisteme.xyz
Thu Sep 16 20:42:10 BST 2021

On 16/09/2021 16:16, Staf Verhaegen (FibraServi) wrote:
> You'll also need a logic analyzer of some sort to look at the outputs of
 > the chip.
Given the relatively low clock frequency, some pretty cheap logic 
analysers can be used (usually just a mcu with an input buffer chip 
topology). My Cypress-based one can apparently sample at 24Mhz, but 
haven't confirmed (only tested with 8MHz so far). The Pulseview software 
supports a lot of different hardware (with additional drivers).

> I think all signal input driving and logic output capturing could be 
> combined on one FPGA with enough pins and 3.3V compatibillity.
> (non-exhaustive list of) Things to drive:
>   * clock reference for PLL
>   * Clock multiplier selection for PLL
>   * reset
>   * JTAG
>       o Test outputs directly with boundary scan
>       o drive internal memory mapped peripherals directly without
>         needing CPU
>       o test on-chip memory; load programs into it
>   * GPIO
Such a tester system could probably fit into an ice40 fpga... although 
my TinyFPGA BX only has a 16Mhz clock, so from my end could only do 
"low-speed" testing.

I do also have a DE0 Nano dev board with a Cyclone 4 fpga, 50Mhz osc, 
8-chan 12-bit ADC. Only issue is that it requires proprietary toolchain 
for synthesis, PnR, bitstream generation.
Absolute ton of available I/O however...


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