[Libre-soc-dev] Testing Libre-SoC 0.18um test chip.
luke.leighton at gmail.com
Thu Sep 16 15:07:58 BST 2021
On September 16, 2021 1:33:23 PM UTC, "Staf Verhaegen (FibraServi)"
<staf at fibraservi.eu> wrote:
>Currently the silicon for the Libre-SoC has been produced and now the
>dice will be packaged.
>I am happy to let other people take on this testing task. So let's
>discuss here if some of you may want to take on this task. I will get
>almost 160 packaged chips. Attached is the package footprint. I also
>socket available that I can send to someone.
i can do one, i really need to be involved, esp. having done the HDL.
my friend tried tracking down the socket, if there are other people
willing to try then we *might* be able to use my friend to buy them
direct from HK or TW.
no, soldering is *not* ok, here! it could damage the ASIC and the
limited quantity means that is not an acceptable risk to take.
>In original project there was a budget of €5400 for the testing task.
do you know what other components are needed (from scratch)?
* three PSUs (3.3v, 1.8v, variable for the PLL)
* and a digital clock of some kind, at least?
an FPGA i assume may potentially useable to generate clock signals,
although ensuring they are stable and shielded will be fun over jumper
cables, a shielded breakout cable should be fine, and it is only what,
24 mhz anyway.
hmm, what about LIP6.fr?
Dimitry, Jean-Paul, Marie-Minerve: would you be interested to try to
test one of the ASICs? particularly, Professor Galayko, the PLL?
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