[Libre-soc-dev] LibreSOC Implementation on arty7 fpga dev boards.

lkcl luke.leighton at gmail.com
Wed Oct 6 15:34:14 BST 2021

varun please take care to always reply to the list.  always hit "reply all".

On October 6, 2021 1:55:08 PM UTC, varun mohan <varunmadhavam at gmail.com> wrote:
this is what I did for now.

1> checked the git logs as you suggested.

commit 06cb49af3734c6c9f2222e235db0f403041001fc     <----- The commit
we want...!???

i said, version you already had was ok (in the list)
xc7a35tcsg324-1 -x arty.xdc > /dev/null

a7-a35t.  you've not passed the correct a7-a100t argument but that can be dealt with later.

ERROR: Conflicting init values for signal 1'0
(\test_issuer.ti.jtag.dmi0_datasr_update_core = 1'0 != 1'x).

this is because you have the wrong version of yosys for nmigen to work with.

check again the wiki page i sent 12 hours ago and use the yosys version from that.

check with Las on #libre-soc IRC because he got it working recently.

i use this:

yosys --version
Yosys 0.9+4052 (git sha1 a58571d0, clang 9.0.1-12 -fPIC -Os)

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