[Libre-soc-dev] LibreSOC Implementation on arty7 fpga dev boards.

[Luke Kenneth Casson Leighton]

On Tue, Oct 5, 2021 at 2:40 PM varun mohan <varunmadhavam at gmail.com> wrote:
>
> HI Team,

Hi Varun, nice to hear from you.

> We are trying to implement  liberSOC on arty 7 fpga boards using the
> repo https://git.libre-soc.org/?p=libresoc-litex.git;a=summary

this is established as a submodule of the soc repo.  you *can* use it
independently, but only once the other software dependencies are
installed.  those can be set up with the devscripts procedures if
you've not already done so

https://libre-soc.org/HDL_workflow/devscripts/

you will also need to install litex: i'm not going to go through that,
you should be able to find the intsallation procedures online.

>. We
> have successfully installed the symbiflow toolchain and can
> successfully generate bitstreams for arty7 fpga dev boards.

brilliant.  that's a really good first step.

> Currently,
> the above-mentioned repo does not support arty7 boards.

yes. i bought one 2 months ago and haven't had time to use it.

> We would like
> some help to adapt the repo so that libreSOC can be implemented on
> arty7 boards using the symbiflow toolchain. Can anyone point to
> resources/materials for the same..!?

right.  ok - and this is why i asked you to contact us on the mailing list:
you're going to need to do some (very short) actual development to
get it running.

see here:
https://bugs.libre-soc.org/show_bug.cgi?id=654#c9

that shows you a link to *someone else's* instructions on how to do this.
obviously, you don't want the RISC-V toolchain.  skip that.

the key step is here:

    Generate the bitstream:
    cd litex/litex/boards/targets && ./arty.py --toolchain symbiflow
--cpu-type vexriscv --sys-clk-freq 80e6 --b

this you will need to ADAPT based on this:

    https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=README.txt;hb=HEAD#l14

  14 ./versa_ecp5.py --sys-clk-freq=55e6 --build
  15 ./versa_ecp5.py --sys-clk-freq=55e6 --load

now, that file versa_ecp5.py was *originally* based on using the
*litex* versa_ecp5.py
code:

https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/lattice_versa_ecp5.py

you will need to *ADAPT* the libresoc-litex versa_ecp5.py so that it
creates an *ARTY* platform instance *NOT* a lattice *versa_ecp5*
platform instance, by comparing the above litex-boards file with
the below litex-boards file:

https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/digilent_arty.py

by comparing the DIFFERENCEs between those two files (their respective
BaseSoC) you will achieve what you want.

this is *not* a difficult task if you are an experienced python programmer.
it should be well under 45 minutes of work and *only* result in around
40-50 lines of code, absolute maximum.

if you believe it to be otherwise then *stop* and reconsider, and ask
here for further advice.

you should be starting with "import litex_boards.targets.digilent_arty as arty"
followed by creating a class ArtyTestSoC(arty.BaseSoC) exactly as is done
at line 27:

27 class VersaECP5TestSoC(versa_ecp5.BaseSoC):

and the arguments should be obvious and self-explanatory from there.

once you have that class it should be natural and obvious that the
next step is to instantiate an instance *of* that class, further down
the file:

https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=versa_ecp5.py;h=a8f2455ed6d43f8809d1c44833aa5d1889443789;hb=42f7357660b245c4491297d24eebc28b4ac2c21f#l128

do not be concerned that it is named "versa_ecp5.py", i will rename it later
to "fpga.py" or something.

sorry i cannot do this for you, i have too many other things to do: i can
however help you through it.

it would be good if you could submit this as a patch for inclusion
in libresoc-litex, or if you can review the Libre-SOC Charter, let me
know if you are ok with it, and then send an ssh public key, and
i can grant you access to git.libre-soc.org repositories.
https://libre-soc.org/charter

best,

l.