[Libre-soc-dev] PLL integration

[Luke Kenneth Casson Leighton]

HA!
sorted.
https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/47


(coriolis2)lkcl at fizzy:~/soclayout/experiments9$ git diff pll.py
diff --git a/experiments9/pll.py b/experiments9/pll.py
index ec31755..68a3bf6 100644
--- a/experiments9/pll.py
+++ b/experiments9/pll.py
@@ -226,6 +226,14 @@ def _load():
             'out_v': Net.create(cell, 'out_v'),
         }

+        # set net directions
+        nets['ref'].setDirection( Net.Direction.IN )
+        nets['a0'].setDirection( Net.Direction.IN )
+        nets['a1'].setDirection( Net.Direction.IN )
+        nets['div_out_test'].setDirection( Net.Direction.OUT )
+        nets['vco_test_ana'].setDirection( Net.Direction.OUT )
+        nets['out_v'].setDirection( Net.Direction.OUT )
+
         # create series of stepped pins
         x = space*20
         wid = space

---
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On Thu, May 27, 2021 at 1:09 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> i know what it is: it's that there's no temporary / intermediary signal.
> i connect the PLL wires *directly* between two modules, and this is
> confusing blif2vst.
>
> i can fix it by creating an intermediate wire in test_issuer.
>
> l.
>
>