[Libre-soc-dev] PLL integration

[Luke Kenneth Casson Leighton]

On Thu, May 27, 2021 at 10:05 AM Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr>
wrote:

>
>   Ha. No, I was meaning "in the rest of the test issuer"...
>
>   The PLL may be one of the most safe part of the chip. It has been
>   completely simulated at spice level (and proved ok). And Dimitri has
>   a long experience in those kind of design.
>

which is fantastic to hear


>   Now that I also have manually and one by one checked the connexions
>   I'm pretty confident that it is working.
>

ok, so what i mean is: testing its connections in simulation is tricky
(needing to use a VBE model not the actual SPICE in e.g. verilator
simulations)

it's not Dimitri's work that is of concern, it's yosys handling of
blackboxes.

i currently have this in the output from the build:

  o  Protect external components not useds as RoutingPads.
  o  Running global routing.
  o  Back annotate global routing graph.
     [  0] nets:[ERROR] Diskstra::load(): Net
"core.subckt_12347_test_issuer.ti_coresync_clk" do not have a driver.

which, oink, i'm reviewing the...

ahhh, the wrapped PLL has had the outputs all turned into inputs:

  component cmpt_wrappll
    port ( clk_24_i   : in bit
         ; clk_pll_o  : in bit
         ; pll_test_o : in bit
         ; pll_vco_o  : in bit
         ; clk_sel_i  : in bit_vector(1 downto 0)
         ; vdd        : linkage bit
         ; vss        : linkage bit
         );
  end component;

this is despite the blackbox clearly saying they are outputs:

(* blackbox = 1 *)
module pll(ref , div_out_test, a0, a1, vco_test_ana, out);
  input a0;
  input a1;
  output div_out_test;
  output out;
  input ref ;
  output vco_test_ana;
endmodule

and in the verilog (libresoc.v) they are clearly outputs:

(* \nmigen.hierarchy  = "test_issuer.wrappll" *)
(* generator = "nMigen" *)
module wrappll(clk_24_i, pll_test_o, pll_vco_o, clk_sel_i, clk_pll_o);
  input clk_24_i;
  output clk_pll_o;
  input [1:0] clk_sel_i;
  output pll_test_o;
  output pll_vco_o;
  pll real_pll (
    .a0(clk_sel_i[0]),
    .a1(clk_sel_i[1]),
    .div_out_test(pll_test_o),
    .out_v(clk_pll_o),
    .\ref (clk_24_i),
    .vco_test_ana(pll_vco_o)
  );
endmodule