[Libre-soc-dev] PLL integration

[Jean-Paul Chaput]

On Wed, 2021-05-26 at 11:14 +0100, Luke Kenneth Casson Leighton wrote:
> JP you definitely need to stay up-to-date on latest soclayout. currently
> 
> https://git.libre-soc.org/?p=soclayout.git;a=commit;h=689f3552a1d8198759581dadf0bc71227076fcbc


  I am. I even made a fresh "git clone" to be sure I have the up to date
  pristine contents.
    It very difficult (verging on impossible) to develop/debug Coriolis,
  or any tool for that matter, if the test cases (in our case, netlists)
  moves under my feets ever so slightly.
    So I progress by leaps between Coriolis and soclayout :
    1. All others things constants, add features & debug Coriolis.
    2. At Coriolis constant, update to the latest soclayout.
    And when switching between 1 --> 2 I keep two seperate git
  repositories of soclayout (the old for 1. and the freshly cloned
  for 2). So I can port one by one with checking every changes I
  made in soclayout.

  In experiment9, we now also have three flavors :
    1. experiment9/  : classic symbolic with Nsxlib.
    2. experiment9/freepdk_c4m45/ : FlexLib on FreePDK45.
    3. experiment9/tsmc_c180/ : Flexlib on TSMC 180nm.

  I have used Yosys 0.9 git 049e3abf9baf795e69b9ecb9c4f19de6131f8418.

  And got :
    1. wrappll wrap_pll_clk_sel_i only "half connected" (bit 1 stuck
       to zero in the BLIF file).
    3. Exact same error as for 1.
    2. Yosys do not complete :

 52  Yosys 0.9+4008 (git sha1 UNKNOWN, gcc 4.8.5 -fPIC -Os)
 53 
 54 1. Executing Verilog-2005 frontend: pll.v
 55 Parsing Verilog input from `pll.v' to AST representation.
 56 Generating RTLIL representation for module `\pll'.
 57 Successfully finished Verilog frontend.
 58 
 59 2. Executing Verilog-2005 frontend: spblock_512w64b8w.v
 60 Parsing Verilog input from `spblock_512w64b8w.v' to AST representation.
 61 Generating RTLIL representation for module `\spblock_512w64b8w'.
 62 Successfully finished Verilog frontend.
 63 
 64 3. Executing Verilog-2005 frontend: ls180.v
 65 Parsing Verilog input from `ls180.v' to AST representation.
 66 Generating RTLIL representation for module `\ls180'.

 ...
794 Used module:                 \dec_DIV
795 Used module:                     \dec_rc$154
796 Used module:                     \dec_oe$155
797 Used module:                     \dec_bi$157
798 Used module:                     \dec_ai$156
799 Used module:                     \dec$153
800 Used module:                         \DIV_ERROR: Module `test_issuer' referenced in module `ls180'
                                                     in cell `test_issuer' does not have a port named
                                                     'sram4k_3_wb__err'.


  What am I missing ?


> then see experiments9/build_full_4ksram.sh
> 
> https://git.libre-soc.org/?p=soclayout.git;a=blob;f=experiments9/build_full_4ksram.sh;hb=HEAD
> 
> note that it now uses VERILOG not ilang/rtlil
> 
> corresponding Makefile also slightly updated.
> 
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