[Libre-soc-dev] PLL integration

[Luke Kenneth Casson Leighton]

ok Jean-Paul i've got as far as i can (temporarily) get,
i will need to create a (fake) PLL cell similar to the (fake) SRAM
cell to get further.

i have added functions to the (fake) FreePDK45 doDesign.py which
search through the cell path names, you *DO NOT* need to manually
name then rename then rename again then change yet again each
and every laborious time.

https://git.libre-soc.org/?p=soclayout.git;a=blob;f=experiments9/freepdk_c4m45/doDesign.py;h=4dd8afd3daec0024060ba5e1348def4ebd6e3f1c;hb=a8e2848b2a68ea284f8f066ca22142a25c698dc6#l108

instead of subctk_NNNN_name1.subctk_MMMM_name2.subctk_OOO.subctk_PPPP

just

name1.name2.name3.

the function will find exactly what you want, down each sub-component path.

l.