[Libre-soc-dev] microwatt / libresoc dcache

[Luke Kenneth Casson Leighton]

On Monday, May 10, 2021, Benjamin Herrenschmidt <benh at kernel.crashing.org>
wrote:

> 48 bits of address-compares?  48x XOR gates (10 gates per XOR), times
> > 64, that's 31,000 gates!  woo!
>
> Euh... no, it's a set associative TLB, not a CAM at all.


tck, tck.... ah yes
https://ars.els-cdn.com/content/image/3-s2.0-B978012800056400008X-f08-09-9780128000564.jpg

ok.  so the LSBs are treated as the lookup, meaning a standard 1R1W
SRAM/BRAM could be used. and that should be single cycle, no problem.

nice.

which makes me curious as to what the heck is going on if timing there is
so critical.

l.



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