[Libre-soc-dev] [OpenPOWER-HDL-Cores] microwatt / libresoc dcache

[Benjamin Herrenschmidt]

On Sat, 2021-05-08 at 15:30 +0100, Luke Kenneth Casson Leighton wrote:
> https://github.com/antonblanchard/microwatt/blob/4a8ab3331c93124bac92776cb2112a506a272592/dcache.vhdl#L23
> 
> -- L1 DTLB entries per set
> TLB_SET_SIZE : positive := 64;
> 
> oof, that's a hell of a lot, paul :)  that's a 64-entry CAM, what...

It's not a CAM no. It's a 64 entry RAM. The number of ways is the "CAM"
size (not really a CAM either mind you). Also those are just defaults,
the real values are passed as generics from above and can thus vary
depending on the implementation.

> 48 bits of address-compares?  48x XOR gates (10 gates per XOR), times
> 64, that's 31,000 gates!  woo!

Euh... no, it's a set associative TLB, not a CAM at all.

Cheers,
Ben.