[Libre-soc-dev] [OpenPOWER-HDL-Cores] microwatt / libresoc dcache

[Benjamin Herrenschmidt]

On Fri, 2021-05-07 at 03:54 +0100, Luke Kenneth Casson Leighton wrote:
> as best i can tell, of reading VHDL, that means that when
> ADD_BUF=true
> there is not a one-clock delay on rd_data output, there is a *two*
> clock delay.

Sort-off yes. It enables the Xilinx FPGA BRAM output buffers which
help tremendously with timing. I couldn't make timing without this
on the Arty back when I wrote that :)

Cheers,
Ben.