[Libre-soc-dev] [OpenPOWER-HDL-Cores] microwatt / libresoc dcache

[Benjamin Herrenschmidt]

On Fri, 2021-05-07 at 09:18 +1000, Paul Mackerras wrote:
> On Thu, May 06, 2021 at 08:24:28PM +0100, Luke Kenneth Casson Leighton wrote:
> > allo again paul,
> > 
> > for reference here is dcache.py:
> > https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/dcache.py;hb=HEAD
> > 
> > pretty much near-identical to dcache.vhdl, one major difference: the bottom
> > 3 LSBs of the address are *not* copied onto the WB bus (as previously
> > discussed, a 32 bit address @ 64 bits wide data must put *29* MSBs onto the
> > WB Bus, *not* the full 32)
> 
> Right, that's something we need to fix throughout microwatt.

Yup, I had a bit of a go at it a while back and it broke all timings
(just removing some wires... go figure). The right approach is to keep
the existing bit numbers but not include the bottom ones.

It's easy to do by editing wishbone_types.vhdl and fixing up the
fallout.

Cheers,
Ben.