[Libre-soc-dev] fighting litex and yosys for pin mapping

[Luke Kenneth Casson Leighton]

i've spent the past week dealing with litex and yosys to get the JTAG
boundary scan connected up.

litex provides absolutely no help whatsoever in determining the direction
of wires: it is purely a naive "generator of verilog by outputting text
fragments that happen to be in verilog".

ordinarily, yosys would be useful to help determine whether those
directions are correct... except that there are also *bugs in yosys* which
leave it unable in all cases to correctly determine port direction.

so it's been 4 days to track down the problem (hidden by another problem
that had to be tracked down) followed by 3 days iterating solutions.

i've finally got something that might be correct.

l.

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