[Libre-soc-dev] [RFC] svp64 "source zeroing" makes no sense

[Luke Kenneth Casson Leighton]

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68


On Sun, Mar 21, 2021 at 7:51 PM Richard Wilbur <richard.wilbur at gmail.com>
wrote:

>
> > On Mar 21, 2021, at 13:20, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
> >
> > skip the operations plural.  then repeat on the next iteration, which
> will
> > have unconditionally incremented both srcstep and dststep by 1. from the
> > next iteration it will continue not from the LSB but from where things
> left
> > off.
> >
> > that's incorrect.  the pseudocode is per loop, repeatedly called until
> > either srcstep or dststep hits VL.
>
> So there is a loop with the aforementioned source code as the body?


yes.  single-stepping like this:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/isa/test_caller.py;h=4ed0577c0fd22a52503c818f371d323e82b8ef7c;hb=HEAD#l49

note the call simulator.setup_one() then at line 63 simulator.execute_one().


  That would explain my lack of understanding—I was missing significant
> context.
>
> So does the
> print “    skip”, bin(1<<{src|dst}step)
> statement just serve for debugging purposes and not actually change the
> operation of the code?
>

https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/isa/caller.py;hb=HEAD#l950

https://www.w3schools.com/python/ref_func_print.asp