[Libre-soc-dev] [RFC] svp64 "source zeroing" makes no sense
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Mar 21 19:19:41 GMT 2021
On Sunday, March 21, 2021, Richard Wilbur <richard.wilbur at gmail.com> wrote:
> On Sun, Mar 21, 2021 at 7:09 AM Luke Kenneth Casson Leighton
> <lkcl at lkcl.net> wrote:
> >
> > as i'm implementing the source- and dest- predication zeroing, it's not
> > making sense:
> >
> > if not src_zeroing:
> > while (((1<<srcstep) & srcmask) == 0) and (srcstep != vl):
> > print (" skip", bin(1<<srcstep))
> > srcstep += 1
>
> Does this mean that if we are not doing source zeroing with the
> predication, then we skip the operation on vector elements where the
> source predication mask is 0 from least significant bit up till the
> least significant 1 in the source predication mask?
skip the operations plural. then repeat on the next iteration, which will
have unconditionally incremented both srcstep and dststep by 1. from the
next iteration it will continue not from the LSB but from where things left
off.
>
> > if not dest_zeroing:
> > # same for dststep
> > while (((1<<dststep) & dstmask) == 0) and (dststep != vl):
> > print (" skip", bin(1<<dststep))
> > dststep += 1
>
> This seems to say that if we are not doing destination zeroing with
> predication, then we skip the operation on vector elements where the
> destination predication mask is 0 from least significant bit up till
> the least significant 1 in the destination predication mask?
same corrections, same statement as above.
> In both of the above, what seems to be most important in the
> predication masks is the position of the least significant bit set to
> 1. Any 0 bits above that don't seem to have any effect on skipping
> the operation.
that's incorrect. the pseudocode is per loop, repeatedly called until
either srcstep or dststep hits VL.
rest of writing below is invalid, skipping. sorry, i do appreciate that it
was quite a lot of analysis work you did.
l.
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