[Libre-soc-dev] [RFC] svp64 "source zeroing" makes no sense

[Luke Kenneth Casson Leighton]

as i'm implementing the source- and dest- predication zeroing, it's not
making sense:

       if not src_zeroing:
            while (((1<<srcstep) & srcmask) == 0) and (srcstep != vl):
                print ("      skip", bin(1<<srcstep))
                srcstep += 1

       if not dest_zeroing:
            # same for dststep
            while (((1<<dststep) & dstmask) == 0) and (dststep != vl):
                print ("      skip", bin(1<<dststep))
                dststep += 1

       if src_zeroing and ((1<<srcstep) & srcmask) == 0:
            RA = 0
            RB = 0
       else:
            RA = get_register_RA
            RB = get_register_RB

       result, Condition_Register = calc_operation(RA, RB)

       if dest_zeroing and ((1<<dststep) & srcmask) == 0):
            result = 0
            Condition_Register = EQzero

       store_result(result)
       if Rc=1: store_cr(Condition_Register)


i'm more inclined towards this:

       if (src_zeroing and ((1<<srcstep) & srcmask) == 0) or
          (dest_zeroing and ((1<<dststep) & srcmask) == 0)):
            result = 0
            Condition_Register = EQzero
       else:
            RA = get_register_RA
            RB = get_register_RB
            result, Condition_Register = calc_operation(RA, RB)

*now* that makes more sense, particularly when thought through from LD/ST.

thoughts?

l.

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